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Serial Communication Interface (SCI)
The SCI clock determines the data transmission (baud) rate and can also establish a periodic
interrupt that can act as an event timer or be used in any other timing function. Bits CD11– CD0,
SCP, and SCR[STIR] work together to determine the time base. If SCR[TMIE] = 1 when the
periodic time-out occurs, the SCI timer interrupt is recognized and pending. The SCI timer
interrupt is automatically cleared when the interrupt is serviced. This interrupt occurs every time
the periodic timer times out.
Figure 8-5 shows the block diagram of the internal clock generation circuitry with the formula to
compute the bit rate when the internal clock is used.
F core
Divide
By 2
12-bit Counter
Prescaler:
Divide by
1 or 8
Divide
By 2
STIR
Divide
by 16
CD[11–0]
SCP
SCI Core Logic
Uses Divide by 16 for
Asynchronous
Uses Divide by 2 for
Synchronous
Internal Clock
If Asynchronous
Divide by 1 or 16
Timer
Interrupt
(STMINT)
COD
If Synchronous
Divide By 2
Fcore
bps = 64 × (7(SCP) + 1) × CD + 1)
SCKP
SCKP = 0 +
SCKP = 1 -
where: SCP = 0 or 1
CD = $000 to $FFF
SCLK
Figure 8-5. SCI Baud Rate Generator
As noted in Section 8.6.1 , the SCI can be configured to operate in a single Synchronous mode or
one of five Asynchronous modes. Synchronous mode requires that the TX and RX clocks use the
same source, but that source may be the internal SCI clock if the SCI is configured as a master
device or an external clock if the SCI is configured as a slave device. Asynchronous modes may
use clocks from the same source (internal or external) or different sources for the TX clock and
the RX clock.
For synchronous operation, the SCI uses a clock that is equal to the two times the desired bit rate
(designated as the 2 × clock) for both internal and external clock sources. It must use the same
source for both the TX and RX clock. The internal clock is used if the SCI is the master device
DSP56311 User’s Manual, Rev. 2
8-18
Freescale Semiconductor
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